For the existing flip-chip (FC) or wafer-level chip-scale packages (WLCSP), the soldering points between a chip and a substrate is vulnerable to breaks due to external forces or thermal stresses causing damages to an IC chips leading to internal interconnection failure during drop tests and reliability tests. Therefore, using underfilling material between the chip and the substrate to protect the soldering points are essential to achieve good product reliability. The conventional underfilling method is to dispense an underfilling material along one side of the substrate with appropriate heat to make the underfilling material fluid then flow into the gap between an IC chip and a substrate through capillary attraction.
Vertically stacking a plurality of chips in flip-chip or in WLCSP (Wafer Level Chip Scale package) formats become the major trend in the advanced packaging technologies. Through Silicon Via (TSV) is also implemented as electrical interconnections between stacked chips, however, multi-layer gaps will be formed between stacked chips at different heights above the substrate. Therefore, the conventional dispensing can not be implemented to underfill the gaps between adjacent stacked chips.
As shown in FIG. 1, a conventional 2D chip assembly 110 is implemented to dispose the underfilling material by dispensing. A dispensing head 121 provides and disposes uncured fluids of underfilling material 120 on the substrate 111 along the side of the chip 112 where the dispensed area of the substrate 111 is not covered by the chip 112. The substrate 111 has to be heated to an appropriate temperature to make the underfilling material 120 fluid but without curing. Then through the high mobility at a specific temperature, the underfilling material 120 will fill into the gap between the substrate 111 and the chip 112 by the capillary attraction to encapsulate the interconnect terminals 114 such as bumps. Finally, at an even higher temperature, the underfilling material 120 is cured to complete the chip assembly 110.
However, when there are multi-layer gaps in a 3D IC assembly with different heights from the substrate, the underfilling material can not fill into the multi-lay gaps through the conventional dispensing. Moreover, the temperatures of the underfilling material can not be well-controlled by only heating the substrate since any variations of temperature gradients will have different capillary attraction for underfilling leading to voids trapped in the multi-layer gaps between two adjacent stacked chips where these voids will be expanded and even exploded during high-temperature processes during the manufacture or operation environments leading to serious product reliability issues.